DHRUV64 Microprocessor
Context
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On 15 December, the Ministry of Electronics and Information Technology (MeitY) announced DHRUV64, an indigenous microprocessor.
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Part of India’s push for strategic autonomy in semiconductor design under the Microprocessor Development Programme (MDP).
What is DHRUV64?
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Developer: Centre for Development of Advanced Computing (C-DAC) under MeitY.
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Type: General-purpose 64-bit, dual-core microprocessor.
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Clock Speed: 1 GHz.
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Architecture: RISC-V based, under the Digital India RISC-V (DIR-V) programme.
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Intended Applications:
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Industrial automation
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Telecom infrastructure
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Embedded systems
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Control systems
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Why is it Significant?
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India is a large consumer but not a designer of processors.
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Indigenous processors enhance:
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Strategic autonomy
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Cybersecurity & supply chain resilience
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Control over updates, toolchains, and IP
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Useful for sectors where reliability > peak performance.
DHRUV64: What the Specs Mean
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64-bit design → supports modern operating systems.
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Performance is modest compared to consumer CPUs (no GPUs/AI accelerators).
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Suitable for:
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Telecom base stations
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Routers
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Industrial controllers
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Automotive electronics
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India’s Processor Ecosystem
| Processor | Institution |
|---|---|
| SHAKTI | IIT Madras |
| AJIT | IIT Bombay |
| VIKRAM | ISRO – SCL |
| THEJAS32/64 | C-DAC |
| DHRUV64 | C-DAC |
DHRUV64 is pitched as a platform for startups and academia to prototype systems without foreign dependence.
What is RISC-V / DIR-V?
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RISC-V:
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Open-source instruction set
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No licensing fees
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Modular and customizable
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DIR-V (Digital India RISC-V):
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National programme to build a portfolio of Indian RISC-V processors
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Earlier chips: THEJAS32 (Malaysia fab), THEJAS64 (SCL Mohali)
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What MeitY Has NOT Revealed
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No performance benchmarks (cache, memory, power efficiency).
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Fabrication details missing (foundry, node, yield, reliability).
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Ambiguity in claim of “fully indigenous” (design vs fabrication vs IP).
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No OEM clarity:
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Developer boards
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OS support
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Security & audit features
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Government anchor usage
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Unclear roadmap beyond announcements.
Future Roadmap (C-DAC)
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DHANUSH:
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Quad-core, 1.2 GHz, 28 nm
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DHANUSH+:
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Quad-core, 2 GHz, 14/16 nm (reported)
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Government Schemes Supporting Indigenous Chips
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Chips to Startup (C2S) – ₹250 crore (5 years)
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Design Linked Incentive (DLI) Scheme
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INUP-i2i – access to nano-fabrication & training
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India Semiconductor Mission (ISM):
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10 projects
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₹1.6 lakh crore investment
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Across 6 States
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Way Forward
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Build system-on-chip families
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Strong software & developer ecosystem
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Transparent manufacturing & testing
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Government as anchor buyer
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Goal: Indian chips adopted without high cost or risk
